1. Field of the Invention
The present invention relates to a disk drive equipped with a disk controller for controlling reading and writing of data from and to a disk, and more particularly to an apparatus and method for controlling the inhibition of data writing in the disk drive.
2. Description of the Related Art
In magnetic disk drives (HDDs), a head (magnetic head) is used to read and write data from and to a disk (magnetic recording medium). The reading and writing of data using the head is performed by a head amplifier circuit (head IC) via a signal processing circuit called a read/write channel. In general, recent read/write channels perform digital signal processing called partial response maximum likelihood (PRML) detection. Further, there is a tendency for the frequency of a signal processed by the read/write channel to increase in accordance with increases in the recording density of magnetic disk drives. The higher the signal frequency, the lower the signal quality. In light of this, recent read/write channels perform complex encoding that can compensate for degradation of signal quality.
In a magnetic disk drive equipped with such a read/write channel, the read error ratio is rather low. However, since encoding is very complex, there is a tendency for a signal delay time due to encoding (i.e., an encoding delay time) and another due to decoding of an encoded signal to increase. In a write operation, for example, when a disk controller has output write data corresponding to one sector to a read/write channel, the output of data from the read/write channel is delayed by the encoding delay time. Therefore, until the output of data from the read/write channel to the head amplifier circuit finishes, it is necessary to keep asserted a write gate signal used in the head amplifier circuit (i.e., keep this signal activated). The write gate signal is a signal (write allowance signal) for allowing data to be written to the disk.
The longer the encoding delay time, the more writing of data to a subsequent sector is delayed. For example, assume that one sector is of 512 bytes, and the read/write channel needs an encoding delay time corresponding to the time required to write data of 30 bytes. In this case, the disk controller needs to keep the write gate signal asserted for the time required to write data of 30 bytes, after outputting write data of one sector (512 bytes). In other words, unless the time (encoding delay time) required for writing data of 30 bytes elapses after one sector data is output, the disk controller cannot process data to be written to the next sector. The time interval from the finish of the output of one sector data to the start of processing of the next sector data is called an inter-sector gap.
There is a recent demand for shortening the inter-sector gap that occurs due to encoding delay in the read/write channel. Jpn. Pat. Appln. KOKAI Publication No. 2000-298934 has proposed a technique (hereinafter referred to “prior art”) using two types of write gate signal, i.e., first and second write gate signals. The first gate signal is used by a read/write channel, while the second gate signal is output from the read/write channel to a head amplifier circuit and used by the circuit. This prior art is characterized in that the read/write channel controls the second write gate signal based on the progress of encoding in the read/write channel itself. In the prior art, the read/write channel asserts the second write gate signal until one sector data to be written is completely output. In other words, the read/write channel controls the second write gate signal for the time required to completely output data. On the other hand, the disk controller only outputs data to the read/write channel and controls the first write gate signal corresponding to the data output. Therefore, the read/write channel can control the timing of data writing in a reliable manner, while the disk controller does not have to consider the encoding delay in the read/write channel, and therefore can secure a sufficient time for preparing the writing of data to the next sector.
In the above-described prior art, the timing of outputting the first write gate signal from the disk controller to the read/write channel differs from that of outputting the second write gate signal from the read/write channel to the head amplifier circuit. Therefore, even if the second write gate signal is output when writing of data should be inhibited, the disk controller cannot detect the output timing of the second write gate signal. In other words, since the second write gate signal used by the head amplifier circuit is output from the read/write channel, the disk controller cannot detect the output timing of the second write gate signal.
As a typical time of inhibiting the writing of data, the time of a servo detection mode, set for reading servo data from the disk, is known. Servo data contains position information used to position the head over a target position. In general, servo data contains a servo mark for identifying the servo data. When the head detects the servo mark, a servo identification signal is asserted in accordance with the detection. During the period in which the servo identification signal is asserted, servo data can be reliably read by the head. Therefore, during this period, the read/write channel is switched to a servo detection mode to detect servo data. In other words, servo data is being written to the area on the disk over which the head passes during the period in which the servo identification signal is asserted.
If data is written to the disk for some reason when the second write gate signal and servo identification signal are asserted simultaneously, servo data on the disk is corrupted. However, in the prior art, the first write gate signal that can be monitored by the disk controller is negated before the assertion of the servo identification signal. Accordingly, even if the disk controller monitors the first write gate signal, it cannot detect whether data is written to the disk, during the period in which the servo identification signal is asserted (i.e., during the period in which data writing should be inhibited).